Recent interest in gigabit logic focuses on GaAs because its electron mobility is about six times that in silicon. Since the hole mobility in GaAs is much lower than its electron mobility, complementary circuits using n- and p-channel GaAs devices are not suitable for high speed data processing. Moreover, since there does not exist a natural oxide of good electric properties for GaAs, contrary to the case of silicon, GaAs transistors are of the Schottky barrier or p.sup.+ -n junction field effect transistor types, so called MESFET or JFET. These n-channel transistors require a suitable load element to complete an inverter circuit. In the Parent Application I have taught the use of micro-tunnel diodes as an improved load element.
Other logic functions such as AND, NAND, OR, and NOR gates can be composed from inverters by use of multiple switching elements, either cascaded or in parallel connection. Two transistors in series can be combined into a single dual gate transistor.
In addition to the logic functions just cited, data processing requires memory. Information is being processed in the binary system involving only two numbers "1" and "0" with any other number of the decimal system expressed as a series of "1" and "0". Memory storage of a number involves an array of memory cells each capable of two electric states, one of these states signifying a "1" and the other a "0".
It is well known that a memory element can be composed from two conventional inverters in a so-called flip-flop arrangement. However, the negative current-voltage characteristics of the tunnel diode enables construction of a simpler memory since the current through a tunnel diode may either cause a small, or else a significantly larger voltage drop, depending on whether the diode operates in the so-called tunnel mode, or else in the thermal mode. The thermal mode is found in any p-n junction diode and involves carrier flow over the junction potential barrier by thermal activation when that barrier has been lowered sufficiently by the applied forward voltage. On the other hand, in the tunnel mode, the barrier is crossed by tunneling of electrons from the conduction band to the valence band. Tunnelling requires a very narrow barrier such as exists only in the abrupt junction between highly doped p and n regions.
Early tunnel diode inverter circuits used bipolar transistors rather than field-effect transistors. Furthermore, they operated the tunnel diode under conditions causing fairly large current flow in the thermal mode. This led to accelerated aging as demonstrated by Gold and Weisberg, Solid State Electronics 7, pp. 811-821, 1964. As a consequence, tunnel diode logic and memory circuits have all but disappeared in the last decade until I disclosed in the Patent Application the advantages of combining tunnel diodes with field effect transistors in circuits in which the thermal current through the tunnel diode is restricted to not much above the valley current, thereby avoiding the above-mentioned aging effects. As an example of prior art not recognizing this important principle of operation, I cite Neff et al. U.S. Pat. No. 3,239,695, who teach operating a tunnel diode with a fairly large current which is about equal for the tunnel mode and the thermal mode.
Since modern logic system lay-out increasingly distributes memory among the data processing subcircuits, there is need of a fast, compact, low-power simple memory array compatible and integrated with the data processing. Therefore, it is one objective of this invention to disclose an improved memory cell design involving micro-tunnel diodes and field effect transistors.
It is another objective of this invention to provide an improved memory cell design which is compatible with, and capable of being integrated with, high speed GaAs logic.
It is another objective of this invention to provide an improved production method for circuits requiring field effect transistors of two different threshold voltages.
These and other objectives will become apparent from the following description.